1. Field of the Invention
The present invention relates to a semiconductor memory device and a fabrication method thereof, and in particular, to an improved semiconductor memory device and a fabrication method thereof which is capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming an impurity area around the trench.
2. Description of the Prior Art
FIG. 1 is a plan view of a layout of a semiconductor memory device according to the conventional art, and FIG. 2 is a longitudinal cross-sectional view of the semiconductor memory device in FIG. 1. As shown in these drawings, a semiconductor substrate 1 is formed having a plurality of (N+) impurity areas (2s,2d) on the upper portion thereof 1, and on the plurality of impurity areas (N+) (2s,2d), a gate oxide film 3 is formed. On the gate oxide film 3, a plurality of polysilicon lines 4 are sequentially formed. The polysilicon lines 4 which serve as word lines are formed to cross the plurality of (N+) impurity areas (2s,2d) . And, a polysilicide layer 5 is formed on the polysilicons 4.
In the above-described semiconductor memory device according to the conventional art, since as many capacitors as the (N+) impurity areas (2s,2d) (which are parasitic capacitors) are formed between the (N+) impurity areas (2s,2d) and the polysilicon lines 4 formed on the semiconductor substrate 1, the delay time of the word lines is disadvantageously increased due to the parasitic capacitors, and it is difficult to reduce the size of a cell due to a lateral diffusion of the (N+) impurity areas (2s,2d). Furthermore, since the (N+) impurity areas (2s,2d) serve as the source and drain of a transistor, a semiconductor memory device having the LDD construction is impossible to fabricate.